Lab 1: CMOS Current Mirrors and Single-Stage Amplifiers

-by: Zheng Chen

Last Modified 4/20/97

INTRODUCTION:

This lab exercise introduces some fundamental building blocks for CMOS analog IC design. These blocks include a variety of current mirrors and single-stage amplifiers with active loads.

It is assumed that you know how to use some Mentor Graphics tools like Design Architect, AccuSim II, and IC station. In this lab, we will use Design Architect and AccuSimII to design and simulate a Common-Source Amplifier, a Source-Follower, and a Telescopic-Cascode Amplifier in 0.8 micron CMOS process. You may refer to reference books for thereotical understanding of these amplifiers. Refer to on-line Analog Station Training Book for more details on analog simulation. This lab will cover:

  1. Transistor level design with Design Architect.
  2. Frequency Response Analysis within AccuSim II.

    Transistor level design with Design Architect:

  1. After logging into a workstation in Stocker 301 (barney, lisa, krusty, maggie, marge, or skinner), start running Mentor Design Manager:
      2. % dmgr&

    Invoke DA by clicking on design_arch icon in the tools window.

  2. In DA, create schematic sheet for a CMOS Common-Source Amplifier with active load.
    1. Set the working directory to your $CLASS/parts.
    2. Open a new sheet and give its path as $CLASS/parts/common_source. Use the techniques that you learned before to create a CMOS common-source amplifier shown in Figure 1. You may choose the current source symbol from the Generic Parts menu by selecting the pull-down menu Libraries > MGC Analog Libraries. Other symbols come from the SDL parts menu of the MDK Libraries.
      3. Figure 1. CMOS Common-Source Amplifier
    3. After you connect the symbols, you need to modify their property values by selecting the pop-up menu Property>Modify... or Modify Multiple.... Change the value of the current source to 100 micro amperes. Change the physical feature of PMOS transistors to 4 lambda length and 250 lambda width, which will correspond to 1.6 micron and 100 micron, respectively, in 0.8 micron process. Change the physical feature of the NMOS transistor to 4 lambda length and 125 lambda width. Note that the bulk terminals of the transistors should be connected to VDD (for PMOS) and VSS (for NMOS).
    4. You should know that Q2, Q3, and Ibias construct a simple 1:1 p-channel current mirror. This current mirror provides a high-impedance output load to the amplifier without using excessively large resistors or a large power-supply voltage.
  3. Create schematic sheets for a Source-Follower and a Telescopic-Cascode Amplifier.
    1. Open new sheets for these two amplifiers with name $CLASS/parts/source_follower and $CLASS/parts/tele_cascode. Refer to Figure 2 and Figure 3 to finish them as you did in the last step.

      2. Figure 2. CMOS Source-Follower

      Figure 3. Telescopic-Cascode Amplifier
    2. Source-follower is also referred to as common-drain amplifier, since the input and output nodes are at the gate and source nodes, respectively, with the drain node being at small-signal ground. It is commonly used as voltage buffer. In Figure 2, the two lower NMOS transistors and the current source construct a 1:1 n-channel current mirror.
    3. In Figure 3, the four PMOS transistors and the current source construct a 1:1 cascode current mirror, which has higher output impedance than the simple two-transistor current mirror. The two NMOS transistors are also in a cascode configuration which consists of a common-source-connected transistor (the lower one) feeding into a common-gate-connected transistor (the upper one).

    Frequency response analysis within AccuSim II:

  4. Analog design needs SPICE simulator to do dc, ac, and transient analysis. AccuSim II simulator uses a SPICE-like engine while applying friendly GUI window so that you only click on icons or menus to perform various analyses.
    1. Before invoking AccuSim II, a special design viewpoint should be generated first. Here we are using a batch mode. In a UNIX terminal window, change directary to your $CLASS/parts, where your designs are stored, and type the command:
        2. % sdl_prep common_source 0.8 -verbose

      This will prepare your design for the 0.8 micron MOSIS process. This command creates a design viewpoint (dvpt) called sdl for the common_source part. You may use DVE to view this dvpt. Note the lambda parameter is set to 0.4 micron in the viewpoint.

    2. Invoke AccuSim II in Design Manager on your design $CLASS/parts/common_source/sdl.
    3. Once AccuSim is loaded, you should see your schematic. The first thing that we need to do is to set up the analysis type. Do this using the Setup Analysis icon in the palette menu. Since you will be performing a frequency response analysis, you need to press the AC button in the dialog box for ac analysis. Give 10 points per Decade. Set a start freq of 1KHz and a stop freq of 10GHz. Leave everything else at its default value.
    4. Next, set the input force. Select signal VIN in the schematic window and then use the Add Force icon to add a force. In the dialog box, enter VSS as the Reference signal and set VIN as an AC type force with a Magnitude of 1V and an Offset of 0.9506V, which will set both Q1 and Q2 in the active region.
    5. To open a trace window, select the output VOUT and press the TRACE item on the palette. Tell the simulator to store All of the calculation results by clicking on the ADD KEEPS icon.
    6. Before you can run the simulation, you must tell the simulator what are the models for your P- and N-FETS. You can use any spice models that you like. There is a model file in $MGC_HEP/technology/accusim/hp08fets.mod that we will use. It is based upon a specific MOSIS run in March, 1997.To load the model file, use the pull-down menu File>Auxiliary Files>Load Model Library....
    7. Now click on the RUN menu item on the pallette to run the simulation. You will see the gain (in voltage) in the trace window. To get a dB chart, select first VOUT then VIN in the schematic window, and choose the pull-down menu Results>[Charting Functions] AC>Bode.... In the dialog box, select the A/B buttton to get a VOUT/VIN gain chart as shown in Figure 4. The gain is about 37 dB, which corresponds to approximately 69 V/V. The output is the inverse of the input.

      8. Figure 4. Frequency Response of the Common-Source Amplifier

    8. Once your simulation is working properly, save your setup for later use. Select the pull-down menu File>Simulation>[Save] Setup data only.... In the dialog box, set the Viewpoint button to save your setup to the viewpoint with a Leafname asim_setup.
    9. Exit from the simulator without saving anything.
  5. Perform frequency response analysis for the Source-Follower and the Telescopic-Cascode Amplifier.
    1. Generate the sdl design viewpoints for the two objects.
    2. Start the ac analysis for the Source-Follower from 1KHz and stop at 1GHz. Set VIN with dc 4 V and ac 1 V. For the Telescopic-Cascode Amplifier, start from 0.1Hz and stop at 100MEGHz. Give VB a dc value of 2.5 V. Give VIN dc 0.8364 V and ac 1 V. The Bode charts for these two amplifiers are shown in Figure 5 and Figure 6.
      3. Figure 5. Frequency Response of Source-Follower

      		Figure 6. Frequency Response of Telescopic-Cascode Amplifier
    3. Ideally, the source-follower has the small-signal voltage gain close to unity, but in reality, it is less than unity. In Figure 5, it is -1.39 dB, which corresponds to 0.85 V/V. The telescopic-cascode amplifier is usually supposed to have gain from 60 to 80 dB. However, my design just achieve 45 dB (180 V/V). You are encouraged to try some other physical features for the transistors (especially, the lower NMOS transistor) so as to achieve higher gain. Note that you need to do dc analysis to determine the new offset dc value for VIN if you modify the NMOS transistors. If you can achieve 60 dB, I will give you extra points. This amplifier has -3-dB frequency around 171KHz.

  6. Finish this exercise by closing all Mentor tools.