Lab : Design and Simulation of Operational  Amplifier

-by: Fengjing Qiu

Last Modified 1/10/98


INTRODUCTION:

This lab exercise shows you how to use Mentor graphics tools to design and simulate the analogy circuit. We will choose two CMOS operational amplifiers ( from the textbook Page 754 and Page 768) as the examples. Upon completion of this Lab, you should  be able to design  the Analog circuits with Design Architecture and  analyze them with AccuSim II. This lab will cover:
  1. Setting up environmental variables.
  2. Transistor level design with Design Architect.
  3. Invoking Accusim II
  4. DCOP (Operating Point) Analysis
  5. DC Sweep Analysis.
  6. Frequency Response Analysis.
  7. Monte Carlo Analysis.

Setting Up Environmental Variables:

  1. First of all, you must have an account on the file server homer in order to use Mentor Graphics tools in this lab. You may contact with Mr. Tim Bambeck in Stocker 324 or Mr. John Tysko to get an account.
  2. After logging into a workstation in Stocker 301 (barney, lisa, krusty, maggie, marge,  apu, smithers, rangers, bart, skinner or skinner), you need to modify the .cshrc file by adding the following lines:
    1. setenv MGC_HEP /mg/mgc_hep
      if ( -e /mg/mgc_hep/startups/startup.csh ) then
              source /mg/mgc_hep/startups/startup.csh
      endif
      setenv MGC_WD $HOME/mgc
    The variable MGC_WD defines your Mentor working directory where your design files will be stored by default. You may define it as any subdirectory you like.
  3. After the modified .cshrc file is executed (e.g., you log into your account again), you will find a new subdirectory named mgc under your home directory and two files mgc_location_map and mgc_location_map.custom under mgc. Create the directory called class under  mgc to store your designs. Next, use a text editor to edit the mgc_location_map.custom file. The soft path $CLASS is defined in the file. You need to link the soft path to the directory you just created  by changing the paths. An example is shown below.

  4. # Class homework and projects location
    #
    $CLASS
    /home/homer/1/c/fqiu/mgc/class
  5. Next, run the following command under prompt:

  6.    % /mg/mgc_hep/bin/genmap
    This command will attach the changed file at the end of the mgc_location_map file. All of the above steps setup the environment in order to run Mentor Graphics applications. You only need to do this once when you run Mentor Graphics tools for the first time.
     

Transistor level design with Design Architect:

  1. After logging into a workstation, start running Mentor Design Manager:
    % dmgr &

    You may see two windows in the Design Manager. The left one shows all of the Mentor tools installed in our system, and the right one shows all of the design objects under your working director $MGC_WD. Activate the tools window, and open Design Architect by double clicking on the design_arch icon.

  1. Create the circuit using schematic editor in Design Architect. You may refer to Module 2, Getting Start with Design Architect to learn how to use schematic editor. Use the pull-down menu Help>open Tutorial to first open the on-line helper Bold Browser, then select the training book.
    1. Click on the Open Sheet icon on the session palette. And enter component name: $CLASS/op_amp1 in the dialog box.
    2. Select the pull-down menu Libraries>MGC Analog Library. Click on the  Generic_parts on the right pallet. Then  all of the components in Generic_lib are shown. Select the current source and resistance  from the palette window and place them in the schematic window.
    3. Select the pull-down menu Libraries>MDK Library. Click on the  SDL parts on the right pallet. Then  select the  nmos, pmos, portin and portout from the palette window and place them in the schematic window.
    4. In the right palette window, hold on the right mouse button and select the Display Schematic Palette item in the popup menu to go back to the main menu. Click on the ADD WIRE icon to connect the parts in the editor window as the figure on shows. You may need to move some parts to proper positions.
    5. After you connect the symbols, Unselect all and select the portins and portouts. Select the popup menu Properties>Change Text Values... and enter Vi1, Vi2 and  Vo1, Vo2 as net names in the dialog box. Then click on the portins name NETs to change them to Vi1, Vi2 and click on the portouts name NETs to change them to Vo1, Vo2.
    6. you need to modify their property values by selecting the pop-up menu Property>Modify... or Modify Multiple.... Change the values of the current source to 5 micro ampere. Change the physical feature of PMOS transistors to 4 lambda length and 250 lambda width, which will correspond to 1.6 micron and 100 micron, respectively, in 0.8 micron process. Change the physical feature of the NMOS transistor to 4 lambda length and 250 lambda width. Note that the bulk terminals of the transistors should be connected to VDD (for PMOS) and VSS (for NMOS).
                      1. figure 1 : the schematic of op-amp1
                        figure 2 : the schematic of op_amp2
    7. Check your sheet by clicking the pull-down menu Check>Sheet. If there are any errors, correct them and check again.
    8. Save your sheet. File>Save Sheet. And  finish the op_amp2 as the figure 2. Close the Design Architecture window.

Invoking AccuSim II:

  1. Analog design needs SPICE simulator to do dc and acanalysis. AccuSim II simulator uses a SPICE-like engine while applying friendly GUI window so that you only click on icons or menus to perform various analyses.
  2. Before invoking AccuSim II, a special design viewpoint should be generated first. Here we are using a batch mode. In a UNIX terminal window, change directory to your $CLASS, where your designs are stored, and type the command:
    1. % sdl_prep op_amp1(op_amp2) 0.8 -verbos

      This will prepare your design for the 0.8 micron MOSIS process. This command creates a design viewpoint (dvpt) called sdl for the op_amp1 (op_amp2). Note the lambda parameter is set to 0.4 micron in the viewpoint.

  3. Invoke AccuSim II in Design Manager on your design $CLASS/op_amp1(op_amp2)/sdl.
  4. Before you can run the simulator, you ought to tell the simulator what are the models for your P- and N-FETS. You can use any spice models that you like. There is a model file in $MGC_HEP/technology/accusim/hp08fets.mod that we will use. It is based upon a specific MOSIS run in March, 1997. To load the model file, use the pull-down menu File>Auxiliary Files>Load Model Library....
  5. Next  you will do the op_amp1's DCOP analysis, DC Sweep analysis, AC analysis and Monte Carlo analysis, Please perform these analysises for op_amp2 by selecting the property values.
 

DCOP Analysis:

  1. AccuSim II always performs a DC Operating Point (DCOP) analysis prior to and in addition to any other analysis.  For this lab exercise, you will run a DCOP analysis by itself.  The default analysis type upon invocation of AccuSim II is the DCOP analysis. click on the pulldown menu path setup >analysis, you can see the default analysis is DCOP, close the widow by clicking OK button.
  2. Prior to running any simulations on the op_amp1, you must apply forces to the two input nets, /Vi1 and /Vi2.  Click on the Add Force icon, AccuSim II now displays the Force dialog box. Select the DC force type choice button, enter /Vi1 in the Signal text field, enter the VSS in the Reference field, enter a value of 2V in the Magnitude text field, and execute the dialog box by clicking on the OK choice button. Add force 1.8V in the magnitude text field for the /Vi2.
  3. Setting Up Keeps for a DCOP Analysis. By default, AccuSim II saves only signals you have specified to keep or trace.  With this simple designs and short runs, you can save all nets, pins and instances during a run without paying a significant disk space penalty. Click on the add keeps icon, select the all choice button, and close the window by clicking OK button.
  4. Report the setup. click on pulldown menu path: Report > Keeps, to Report the signals being kept during future analyses ; click on report>force to report the forces you have added to the signals. .Report the current analysis setup using the following pulldown menu path: Report > Analysis Setup
  5. Run the DCOP analysis by click the palette menu Run; and then  List the results of the DCOP analysis in the DCOP list window using the following pulldown menu path: Results > DCOP.

  6. Once your simulation is working properly, save your setup for later use. Select the  pull-down menu File>Simulation>[Save] Setup data only.... In the dialog box, set  the Viewpoint button to save your setup to the viewpoint with a Leafname asim_setup.
 

 

DC Sweep Analysis:

  1. In the Accusim II window,  click on the pulldown menu path setup > analysis, in the setupanalysis dialog box, since the default analysis is DCOP, you should setup the analysis type to DC Sweep, enter the Vi1 in the source or force name, sweeping from 2v to 3V, by 0.1V
  2. Click on the Add Force icon, in  the Force dialog box. Select the DC force type choice button, enter /Vi1 in the Signal text field, enter a value of 2V in the Magnitude text field, enter the VSS in the Reference field, clicking on the OK choice button.
  3. Click on the add keeps icon, select the all choice button as you did before. Report the setup. click on pulldown menu path: Report > Keeps, report>force, report > Analysis Setup    check the value you had set..Run the DC Sweep analysis by clicking on the run menu, To see the (Vo1-Vo2) vs (Vi1-Vi2) chart, click on the OPEN WF PROC    icon to open a waveform processor. We define the y axis as Vo1-Vo2. First select the y icon in the WF processor, then click on V icon for a voltage signal, use the red cross to select Vo1 in the schematic window. You will see an item shown in the dialog box. To add a minus symbol, use the popup  menu in the WF processor and select the - icon. Then click on the V icon again and select Vo2. Now you finish the function for y axis. Next select the x icon, and use the same methods to add the function for x axis.  Then you will get the curves  (Vo1-Vo2) / (Vi1-Vi2),
  4. Remember to save the setup data for later use. Exit from the simulator without saving anything.
 
 

 

Frequency response analysis:

  1. To set up the analysis type by using the Setup Analysis icon in the palette menu. Since you will be performing a frequency response analysis, you need to press the AC button in the dialog box for  ac analysis. Give 10 points per Decade. Set a start freq of 1Hz and a stop freq of 1GHz. Leave everything else at its default value.
  2. Next, set the input force. Select signal Vi2 in the schematic window and then use the  Add Force icon to add a force. In the dialog box, enter VSS as the Reference signal and set VIN as an DC type force with a  Magnitude of 2.5V, and set the signal Vi1 as an AC type force with Magnitude of 1.0V  and an Offset of 2.5V,
  3. To open a trace window, select the output Vo1 & Vo2  and press the TRACE item on the  palette. Tell the simulator to store All of the calculation results by clicking on the ADD KEEPS icon.
  4. Now click on the RUN menu item on the palette to run the simulation. To get a dB chart, select Vo1, Vo2 and Vi1, Vi2 in the schematic window, and choose  the pull-down menu Results>[Charting Functions] AC>Bode.... In the dialog box, set Vo2-Vo1 as A, Vi1-Vi2 as B. Select the A/B button to get a VOUT/VIN gain chart
  5. Save the setup data and exit from the simulator without saving anything.
  6. Finish this exercise by closing all Mentor tools.
 


 

Monte Carlo analysis: