--      
-- swfinal.vhd 
-- Version: v1.1
--

Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;

entity SWFINAL is
	port (
	      CLK: in STD_LOGIC;                        -- clock (36MHz)
         MR:  in STD_LOGIC;                        -- master reset pin
         L,S: in STD_LOGIC;                        -- L-"light", S-"start/stop" of my wristwatch
         ENIN:  in STD_LOGIC;                       -- enable
         RSTIN: in STD_LOGIC;                       -- reset
         RUNIN: in STD_LOGIC;                       -- start/stop ('1' means run)
	      Q3:  out STD_LOGIC_VECTOR (3 downto 0);  -- 10    Sec
	      Q2:  out STD_LOGIC_VECTOR (3 downto 0);  -- 1     Sec
	      Q1:  out STD_LOGIC_VECTOR (3 downto 0);  -- 1/10  Sec
	      Q0:  out STD_LOGIC_VECTOR (3 downto 0)   -- 1/100 Sec
			);
end SWFINAL;

architecture SWFINAL_STR of SWFINAL is

component SWFSM -- U1
    port (
        CLK: in STD_LOGIC;
        MR: in STD_LOGIC;
        L,S: in STD_LOGIC;-- L-"light", S-"start/stop" of my wristwatch
        EN, RUN, RST: out STD_LOGIC-- outputs to monitor "latch enable", "run stop", and "reset" conditions
    );
end component;

component TIMER -- U2
	port (C:   in STD_LOGIC;                       -- clock (100Hz)
	      EN:  in STD_LOGIC;                       -- enable
	      RST: in STD_LOGIC;                       -- reset
	      RUN: in STD_LOGIC;                       -- start/stop ('1' means run)
	      Q3:  out STD_LOGIC_VECTOR (3 downto 0);  -- 10    Sec
	      Q2:  out STD_LOGIC_VECTOR (3 downto 0);  -- 1     Sec
	      Q1:  out STD_LOGIC_VECTOR (3 downto 0);  -- 1/10  Sec
	      Q0:  out STD_LOGIC_VECTOR (3 downto 0)); -- 1/100 Sec
end component;


component CLKDIV2 -- U3
	port (CLK: in STD_LOGIC;
	      MR: in STD_LOGIC;
	      SMCLK : out STD_LOGIC;
	      SWCLK : out STD_LOGIC
	      );
end component;


signal  DATA3, DATA2, DATA1, DATA0: STD_LOGIC_VECTOR(3 downto 0);
signal  SWCLKi, SMCLKi: STD_LOGIC; -- stopwatch and state machine clocks
signal  EN, RUN, RST: STD_LOGIC; -- stopwatch and state machine clocks
signal  ENi, RUNi, RSTi: STD_LOGIC; -- stopwatch and state machine clocks

begin

ENi<=ENIN and EN;
RUNi<=RUNIN and RUN;
RSTi<= RSTIN or RST;

U1: SWFSM
	port map (SMCLKi, MR, L, S, EN, RUN, RST);

U2: TIMER
	port map (SWCLKi, ENi, RSTi, RUNi, Q3, Q2, Q1, Q0);

U3: CLKDIV2
	port map (CLK, MR, SMCLKi, SWCLKi);

end SWFINAL_STR;