--By Lily Li
--3/30/2005

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top_io is
    Port (
        mclk    : in std_logic;
        btn     : in std_logic_vector(3 downto 0);				   --Buttons
        swt     : in std_logic_vector(7 downto 0);				   --Switchs
        led     : out std_logic_vector(7 downto 0);				--LEDs
        an      : inout std_logic_vector(3 downto 0);				--LCDs
        ssg     : out std_logic_vector(7 downto 0)
		 );
end top_io;		   	  

architecture rtl of top_io is
 

	component SWFINAL 
	port (
	      CLK: in STD_LOGIC;                       -- clock (36MHz)
         MR:  in STD_LOGIC;                        -- master reset pin
         L,S: in STD_LOGIC; -- L-"light", S-"start/stop" of my wristwatch
         ENIN:  in STD_LOGIC;                       -- enable
         RSTIN: in STD_LOGIC;                       -- reset
         RUNIN: in STD_LOGIC;                       -- start/stop ('1' means run)
	      Q3:  out STD_LOGIC_VECTOR (3 downto 0);  -- 10    Sec
	      Q2:  out STD_LOGIC_VECTOR (3 downto 0);  -- 1     Sec
	      Q1:  out STD_LOGIC_VECTOR (3 downto 0);  -- 1/10  Sec
	      Q0:  out STD_LOGIC_VECTOR (3 downto 0)  -- 1/100 Sec
	);
   end component;					  
   
   

   
  		 	  
    signal cd		: std_logic_vector(1 downto 0):="00" ;
	signal rst      :std_logic;
	signal mhertz_count	: std_logic_vector(5 downto 0) ;	-- 
    signal khertz_count	: std_logic_vector(9 downto 0) ;	-- 
	signal mhertz_en	: std_logic ;				-- 
    signal khertz_en	: std_logic ;						   
    signal firstTwoNum,LastTwoNum: std_logic_vector(7 downto 0);	 
signal   btn1: std_logic;  
signal   swt0: std_logic;  
signal   swt1: std_logic;  	  
signal   swt2: std_logic;  	
signal   swt3: std_logic;  		
signal   reseti: std_logic;  	 

begin					  
 btn1<=not btn(1);
  --swt0<=not swt(0);
  swt1<=not swt(1);
  swt2<=not swt(2);  
  swt3<=not swt(3); 
  --reseti<=btn(1);					  
  rst<=btn(0);		
  	 
  
  MY_SWFINAL: SWFINAL 
  port map(
	      CLK =>mclk,
           MR=>btn1,
     		L=>swt1,
			S=>btn(3),
         ENIN=>swt2,   					  --swt(2) ='1' to stop
         RSTIN=>btn(2),						--reset
         RUNIN=>swt3,						--swt(3)='1' to stop
	      Q3 => FirstTwoNum(3 downto 0), -- 10    Sec
	      Q2 => FirstTwoNum(7 downto 4), -- 1     Sec
	      Q1 => LastTwoNum(3 downto 0),  -- 1/10  Sec
	      Q0 => LastTwoNum(7 downto 4)   -- 1/100 Sec
			);


-- generates a 1 Mhz signal from a 50 Mhz signal
process (mclk, rst)
begin
if rst = '1' then
	mhertz_count <= (others => '0') ;
	mhertz_en <= '0' ;
elsif mclk'event and mclk = '1' then
	mhertz_count <= mhertz_count + 1 ;
	if mhertz_count = "110010" then
		mhertz_en <= '1' ;
		mhertz_count <= (others => '0') ;
	else 
		mhertz_en <= '0' ;
	end if ;
end if ;
end process ;												

-- generates a 1 kHz signal from a 1Mhz signal
process (mclk, rst)
begin
if rst = '1' then
	khertz_count <= (others => '0') ;
	khertz_en <= '0' ;
elsif mclk'event and mclk = '1' then
	if mhertz_en = '1' then
		khertz_count <= khertz_count + 1 ;
		if khertz_count = "1111101000" then
			khertz_en <= '1' ;
			khertz_count <= (others => '0') ;
		else
			khertz_en <= '0' ;
		end if ;
	else
		khertz_en <= '0' ;
	end if ;
end if ;
end process ;

process(mclk,rst)

begin

if rst = '1' then	
	an<="0000";
	ssg <= "11000000";
elsif mclk'event 	and mclk = '1' then 	 
	if khertz_en = '1' then
		cd(1 downto 0) <= cd(1 downto 0) + 1 ;
	end if ;
	  
	if cd="00" then		
		an<="0111";
		case  LastTwoNum(7 downto 4) is 
			when "0000" => ssg <= "11000000"  ;  
			when "0001" => ssg <= "11111001"  ;	  
			when "0010" => ssg <= "10100100"  ;	  
			when "0011" => ssg <= "10110000"  ;	 
			when "0100" => ssg <= "10011001"  ;	 
			when "0101" => ssg <= "10010010"  ;	 
			when "0110" => ssg <= "10000010"  ;	 
			when "0111" => ssg <= "11111000"  ;	 
			when "1000" => ssg <= "10000000"  ;	 
			when "1001" => ssg <= "10010000"  ;	 
			when others => ssg <= "11000000"  ;	  
		end case ;
		
	elsif cd="01" then	  
		an<="1011";
		case  LastTwoNum(3 downto 0) is 			   
			when "0000" => ssg <= "11000000"  ;  
			when "0001" => ssg <= "11111001"  ;	  
			when "0010" => ssg <= "10100100"  ;	  
			when "0011" => ssg <= "10110000"  ;	 
			when "0100" => ssg <= "10011001"  ;	 
			when "0101" => ssg <= "10010010"  ;	 
			when "0110" => ssg <= "10000010"  ;	  
		    when others => ssg <= "11000000"  ;	 
		end case ;			  	 
		
		elsif cd="10" then		
		an<="1101";
		case  FirstTwoNum(7 downto 4) is 
			when "0000" => ssg <= "11000000"  ;  
			when "0001" => ssg <= "11111001"  ;	  
			when "0010" => ssg <= "10100100"  ;	  
			when "0011" => ssg <= "10110000"  ;	 
			when "0100" => ssg <= "10011001"  ;	 
			when "0101" => ssg <= "10010010"  ;	 
			when "0110" => ssg <= "10000010"  ;	 
			when "0111" => ssg <= "11111000"  ;	 
			when "1000" => ssg <= "10000000"  ;	 
			when "1001" => ssg <= "10010000"  ;	 
			when others => ssg <= "11000000"  ;	  
		end case ;				   			 
		
		elsif cd="11" then	  
		an<="1110";
		case FirstTwoNum(3 downto 0) is 			   
			when "0000" => ssg <= "11000000"  ;  
			when "0001" => ssg <= "11111001"  ;	  
			when "0010" => ssg <= "10100100"  ;	  
			when "0011" => ssg <= "10110000"  ;	 
			when "0100" => ssg <= "10011001"  ;	 
			when "0101" => ssg <= "10010010"  ;	 
			when "0110" => ssg <= "10000010"  ;	  
		    when others => ssg <= "11000000"  ;	 
		end case ;	
	end if;
	
end if;

	end process;
	end rtl;