--      
-- stopwatch.vhd 
-- Version: v1.1
-- 

-- CLK_DIV - Behavioral Model
-- This should ideally divide the 36MHz system clock to 100Hz 
--
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity CLKDIV2 is
	port (CLK: in STD_LOGIC;     -- 36 MHz clock input
	      MR: in STD_LOGIC;     -- reset
	      SMCLK: out STD_LOGIC; -- clock for state machine
	      SWCLK: out STD_LOGIC  -- clock for stopwatch timer
	      );
end CLKDIV2; 


architecture CLKDIV2_BEH of CLKDIV2 is

signal QOUT: STD_LOGIC_VECTOR (18 downto 0);

begin
   process (CLK, MR) 
	begin
	   if MR = '0' then
		L1: for count_value in 18 downto 0 loop 
        		QOUT(count_value) <= '0';
      		end loop L1; 
   	else
		    if (CLK'event and CLK='1') then
	    		QOUT <= QOUT + 1;
		    end if;
	   end if;
   end process;

SWCLK <= QOUT(18); -- using appropriate taps off the counter as divided  	  137hz
SMCLK <= QOUT(12); -- clock outputs

end CLKDIV2_BEH;