Lab 3: Getting Started with ICverify and Lsim

-by: Zheng Chen
-Modified by: Liang Yin

Last Modified 12/31/98


HomeWork 2

Due Date: Jan. 25th, 1999

INTRODUCTION:

This lab exercise introduces how to verify the layout of my_inverter created in the last lab, using Mentor IC verification toolsets. This lab will cover:
  1. Design rules checking (DRC) with ICrules.
  2. Layout versus schematic (LVS) with ICtrace.
  3. Parasitic extraction (PEX) with ICextract.
  4. Post simulation with Lsim.

    DRC with ICrules:

  1. After logging into a workstation in Stocker 301 , start running Mentor IC station:
      2. % ic&
    In the ICgraph window, set working directory to $CLASS by selecting Setup>IC.... Select [Cell] Open to open your layout cell $CLASS/physical_lib/MY_INV for Edit. All the other IC verification toolsets are integrated within ICgraph environment. ICrules is used for design rules checking (DRC).
    1. Click on the ICrules item on the IC palette. You may have a look at which design rules will be checked, by selecting List>Check.... All the rules displayed in the dialog box are defined in the design rules file $MGC_HEP/technology/ic/scmos.rules.
    2. Select the pull-down menu MGC>Setup>Sessions... to set sessions shown as left right tiling. The open transcript window by selecting MGC>Transcript. Active the layout window, and click on the Check item on the palette. You will see all the checking results shown in the transcript window.
    3. If you got design rules violations, scan these violations by selecting [Set Scan to] First and Next, and so on. The Figure 4 in Lab 2 has 5 violations with design rule Metal1 width = 3L.
    4. Correct the violations using layout editing techniques learned in Lab 2.
    5. DRC again until no violation is found. Save your cell. File>Cell>Save Cell.

    LVS using ICtrace (M):

  2. There exists two types of layout versus schematic (LVS) verification, Direct and Mask. In brief, the difference of these two modes is that Direct mode compares the electrical connectivity of a cell layout with a source circuit, while Mask mode compares electrical connectivity of the entire ICgraph hierarchical layout with the connectivity of the source circuit. Direct mode is used to support hierarchy design where you need not to concernn about the inner conncetions of cells at low levels. You just care about that the connections are all right within the schematic level. Here we use Mask mode because this layout is the lowest level cell layout.
    1. If the active palette is still the ICrules palette, select Back to go back to IC palette. Then select ICtrace (M) item. Click on LVS. In the dialog box, enter Report name with $CLASS/lvs.rep and select Source name with $CLASS/parts/my_inverter/lvs (design viewpoint file created in Lab 1). Click on the Setup LVS... button, and change the Recognize Gates option to No in the setup form. Run LVS.
    2. When the LVS check completes, select Report>LVS from the right palette. You will see a cross symbol in the report file, which means that this LVS failed. The reason is that we used 3-terminal FET's in schematic, while the layout involved 4-terminal FET's.
    3. Close the report window by a default right-to-left stroke. Select Logic>Open: to open the schematic design viewpoint. You may cross probe between the schematic and the layout, by selecting nets or instances in the schematic window.
    4. Modify your schematic by openning Design Architect in a UNIX terminal (% da&). Replace the 3-terminal FET's with p-fet-4 and n-fet-4 in MDK library, and connect PMOS FET's bulk terminal (B) to VDD and NMOS FET's B terminal to VSS. Check and save your modified schematic.
    5. Go back to the IC station window. On the ICtrace (M) palette, select Viewpoint>Resync: to update the schematic source. Do LVS again. There should be no errors now. You may use cross probing and highlighting to understand the relation between the layout and the schematic. When you select the net VSS in the schematic window, you may find that the polygon of P-well in the layout window is not highlighted, while the whole substrate is highlighted. This is because the p-well layer is not defined in the design rules. In fact, we are using a 1.2 micron, N-well, two poly, and two metal SCMOS process. However, the additional p-well polygon will not effect the final design.

    PEX with ICextract (M):

  3. ICextract permits a parasitic extraction from layout. You can either have a netlist for Lsim or HSPICE and /or a backannotation file attached to your schematic or both. In this exercise, we will create only an Lsim netlist.
    1. To prepare for extraction, be sure your cell is reserved for edit. Go to the ICextract(M) palette menu.
    2. Select Lumped from the palette menu to display the extraction dialog box. Lumped extraction will treat each distinct net as one lumped capacitor and/or resistor. In the dialog box, enter Export file name with $CLASS/pex.rep and select Yes for Netlists. Enter netlist name with $CLASS/lsim/my_inverter.N (you may create the subdirectory lsim before) and ground name with VSS, and select LSIM for Format. Execute this dialog box.
    3. Use MGC>Notepad>Open>Read Only... to open the report file $CLASS/pex.rep and the netlist file $CLASS/lsim/my_inverter.N.
    4. Close the IC station.

    Post simulation with Lsim:

  4. Lsim is a comprehensive mixed-signal, multi-level simulator. For more details, refer to the Bold Browser on-line document Lsim User's Manual, especially Chapter 2 Tutorial.
    1. In a UNIX terminal window, change directory to $CLASS/lsim, where the netlist file my_inverter.N is stored. Type the following command:
        2. % Lsim -mode adept my_inverter.N &
    2. Once in Lsim, you should see your 2 nodes, IN and OUT. To set values to the input signals, select IN with the left mouse button. You can either use the keystroke l to set the value low or use the keystroke h to set the value high.
    3. After the initial value is established (e.g., low on IN), you can simulate your circuit for a few clock cycles. To do so, just type s simulate in one step interval, which is displayed in the Status Window and is set to a default value of 1 ns. You may change the default interval by clicking on that text bar.
    4. Toggle the value of IN several times. You may see the rise and fall edges of OUT are not strictly vertical. In the Probe Display window, select the popup menu Display>zoom to fit. The delay for this inverter is less than 0.1 ns.
    5. You may explore more functions of Lsim according to the Tutorial.
    6. Exit Lsim by closing the application window. Lsim provides a history mechanism. So every command you typed in the session will get logged to a file Lsim.history. This file will need to be copied to another name like my_inverter.i for a later use.
  5. Finish this exercise by closing all Mentor tools.

[ VLSI EE415 Lab Assignment ]