Last modified: Jan, 2008
The new webpage was created by Haibo He, Yinyin Liu and Lily. If you have any suggestions or comments regarding this lab materials, please send your email to haibohe@bobcat.ent.ohiou.edu. Thanks.
Basawaraj
323 Stocker Center, Mailbox #94
Tel: (740) 593-4995
Email: bb593707@ohio.edu
Office Hours:-
Tuesday 10:00 AM to 1:00 PM, Stocker Room 323
Friday 3: 00 ~ 5: 00 pm
Stocker 307 is reserved for the Winter Quarter during these hours.
Note:
* For those who are doing Mentor Graphics labs for the first time: Make sure you set up the environment as described in the Requirements section.
In this quarter, we will learn how to implement IC design by using the Mentor Graphics tools, IC Station and other related tools. IC Station tools provide you with the capability to design full custom cells and mixed standard cell and block hierarchical layouts. The labs in the quarter will cover the whole process of full custom IC design, we will also try to cover the some automatic design process if applicable.
The purpose of the labs is to make you familiar with the IC design method as well as design concept. It is not enough for you to just follow the instructions published on the web pages, although it is the only way that you can finish your lab assignments successfully. The Mentor Graphics tools can be used for industry use. It is more complicated than what we need in these labs. So be careful your design process, menu commands and dialog options. You are encouraged to read the help documents, which can be opened by just typing mgcdocs &under cshell. These help documents can help you to understand the meaning of the design process and the meaning of every step. Some simple help messages will also be available on the web (http://www.mentor.com/supportnet/). You will be tested at the end of every lab based on these design concepts and skills.
Before going ahead, please make sure that you have set up the environmental variables properly via the instructions in the requirement of VLSI Lab. In this lab exercise, you need the soft path $CLASS to be set in advance. For example, you may link $CLASS to $HOME/mgc/class ($HOME must be the full path like: /home/<your name>, and you should make a subdirectory class under mgc).
Requirement
There are 5 labs to finish within the quarter. One lab is desired to be finished each week. Then you will have enough time on your project. There is no lab report required, but you have to show the results to TA during the lab time after you complete.
Very Important:
After you log in the SOLARIS 10, please type the following command first in the command window before you run any Mentor Graphics software:
(1) % xhost +p3
(2) % ssh p3
note: it will ask you for password again, just input your password
(3) % setenv DISPLAY <hostname>:0
note: for example, if your host name is bin00010, type in:
% setenv DISPLAY bin00010:0
Lab1: Getting
Started with Design Architect and AMS
simulation
Lab2: Getting
Started with ICGraph
Lab3: Getting
Started with DRC,
LVS, PEX and post-layout simulation
Lab4: ASIC Design Flow I
Lab5: ASIC
Design Flow II
Design Project: suggested design projects are listed below.
Grading: (total 50%)
|
Laboratory Assignments (20%) |
|
Design Project (30%):
Design simulation and layout (20%) |
Suggested Design Projects for VLSI Lab
Arithmetic and Logic Subsystems:
A1.Bit Slice ALU.
A2. 8-bit
Serial Multiplier: with Booth's recording.
A3. 6*6 Booth
Multiplier
A4.4x4
Parallel Multiplier: in array or tree configuration.
A5. Incrementer/Decrementer.
A6. Comparator: of two n-bit numbers. (i.e. expandable architecture)
A7. 4-bit
Baugh-Wooley Multiplier
A8. 8-bit
Logarithmic Multiplier
A9. 4-bit
Braun Multiplier
A10.4-bit
Parallel Full Adder: with carry-look-ahead.
A11. 8-bit
Transmission-Gate Adder
A12. 4-bit
CLA Adder Using Cross-Coupled Domino Logic
A13. 8-bit
Carry Skip Adder
A14.8-bit
Carry-Select Adder
A15.8-bit
Brent and Kung Adder
A16.CRC (cyclic
redundancy checker ) .
A17. 16-bit Fast 2’s Complement Converter
A18. Fast 32-bit Parallel Comparator
A19. 16-bit
Serial-Parallel multiplier
Memory Subsystems:
B1.Dual-Port Static Register.
B2.Static Random Access Memory: with cross-coupled inverters.
B3.Dynamic Random Access Memory: 3- or 4- transistor cells.--
B4.Content
Addressable Memory.
B5.Stack: Last-in, First-out Memory.
B6.Queue: First-in, First-out Memory.
Control Subsystems:
C1. Writable PLA.
C2.
Serial-to-Parallel or Parallel-to-Serial Converter.
C3. BCD-to-Binary or Binary-to-BCD Converter: for bit serial applications.
C4. 8-bit
Barrel Shifter.
C5.
Pseudo-Random Sequence Generator: for built-it self test.
C6. A control lock circuit using PAL.
C7. Signature Analyzer
C8.
Binary Counter (ex. 8 bit loadable counter)
C9. Finite State Machine.
C10. A Mod-100 Decimal Counter
C11. 4-phase Clock Generator
C12. 8-Bit
Parity Generator/Checker
C13.
4-bit Universal Shift Register
C14. Binary-to-Gray code Converter
C15. BCD-to-4bit Gray code Converter
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