Lab 7 - ASIC Design Flow III (cont.)

Lab 6: ASIC Design Flow III

Last modified: 1/05/06

INTRODUCTION:

In this lab exercise you will develop a simple 4-bit static random access memory (SRAM) with simultaneous read/write capability. The design flow introduced in this lab may be used in your design projects since it allows very fast schematic->layout conversion with the ability to use your own pre-designed components. You should be familiar with all preceding labs to finish this one.

Design flow:

1) Creating schematics

2) Creating viewpoints

3) Creating layouts for separate components and the final SRAM chip

1. Creating schematics

1. Invoke the Design Architect. Set your working directory to /home/<your user name>/mgc/class.

2. Use the standard ADK library to create schematics for the 2-to-4 DeMUX (name as demux2to4), 4-by-1 bit memory cell array(name as mem4by1), and the final 4-by-1 SRAM chip(name as mem4by1chip). Refer to the screenshots below (Fig.1 - Fig.3) to get an idea on schematic. ADK library is accessible by going to ADK IC Libraries on the Schematic Edit palette.

3. After finish the schematic of DeMUX and memory cell array, create symbols (like you did in Lab 1) for them. You may create a symbol for the final SRAM component as well for your future use (but you will not need it in this lab). Though it is up to you to name the components, in this lab, names demux2to4, mem4by1, andmem4by1chip are used. Add the COMP and MODEL properties when you create the symbols. For example, if your demux is named as demux2to4 then:

Property Name: COMP, Property value: demux2to4, and select Visible

Property Name: MODEL, Property value: demux2to4, and select Hidden

refer to lab 1 for how to create symbols.

4. Creation of the demux is a straightforward task since it contains only NAND and NOR gates and some inverters. The demux presented in Fig. 1 is a 2-to-4 demux with active low outputs and an active low enable input.

Memory cell array consists of 4 invering transparent latches and 4 tri-state output buffers. Notice that memory cell array has separate control signals for read and write addresses. This will allow for simultaneous read/write operations. You can convert this simple architecture into a Dual-Port SRAM simply by adding an additional tri-state buffer per latch output (You do not need to do this now :) ). Dual-Port SRAMs are used in parallel computer architectures as they allow for two simultaneous read operations and one write operation. Some arbitration logic may be needed if overwriting data that is currently being read is not allowed.

Since there is no tri-state output buffer in this software, you can have two options here:

(1) You should create your own tri-state symbol first. Following Fig shows the transistor level schematic of the tri-state, and you need to create this symbol first before you can create the 4-by-1 bit memory cell. (2) For simplicity, you can use an AND gate to replace the tri-state. However, this is not the correct memory schematic. You are doing this way only to simplify this design, and get familiar with the hierarchical layout design flow.

Fig.1 2-to-4 line demultiplexer

Fig.2 4-by-1 bit memory cell array

Fig. 3 4-by-1 bit SRAM

2. Creating viewpoints

Type "adk_dve" followed by the full path of the design in the UNIX command window to create all the viewpoints of all the component cells.

3. Creating layouts for separate components and the final SRAM chip

1. First, you need to create layouts for the deMUX and your memory cell array (Note: if you using your own tri-sate symbol design in the schematic, you need to create the layout of the tri-state first). Follow steps introduced in Lab 5 to finish this part. You should end up with two layouts similar to the ones shown in Fig. 4 - Fig. 5. Perform extraction of parasitics using Calibre(PEX) as you did in Lab 3.

At any point in time during your design, if the IC Station crashes you have to delete all files related to the component you were designing in the /home/<your user name>/mgc/class/physical_lib directory using MGC->Design Management->Delete Object menu. If this fails, i.e. you get a message saying that some object cannot be deleted, start a console and manually delete those files suing UNIX`s rm command.

Fig. 4 Layout for the 2-to-4 line deMUX

Fig.5 Layout for the 4-by-1 bit memory array

2. The next step is to re-use these layouts in the IC Station to build higher level design. We will use the Auto Floor Planner and the IC Blocks tool to automatically place all components and integrate them into one layout. Start IC Station and click on Create Cell. After filling all the empty fields like you did in Lab 5 click on the Logic Loading Options button of the Create Cell window. You will see another window like in Fig. 6. Here, choose Preserve Subcell Layout (ECO) option. If you skip this step IC Station will DESTROY all existing cell layouts that you created! In the Viewpoint Directory prompt enter the directory where your final component schematic is located, e.g. /home/<your user name>/mgc/class/lab6/mem4by1chip. You may leave Layout Directory in the default state in which case all the temporary files will be placed into the current working directory (hopefully you have set it to /home/<your user name>/mgc/class/physical_lib :) ). Leave all other settings at their default states and click on OK to close this window and then the Create Cell window.

Fig. 6 Logic Loading Options window

3. You should get an empty window in your IC Station. If you get a message saying that cells in some library cannot be dynamically loaded go to File->Library->Attach and select the needed library ($ADK/technology/ic/process/ami05). Do not forget to reserve your cell for editing before doing that.

4. Do the Auto floorplan. On the IC Palettes -> ICBlocks -> Place & Route palette click on Blocks and accept all the defaults. This should place the two demuxes and the memory cell array. Now, on the same palette select StdCell which will place the four inverters that we had on the final schematic for the SRAM chip. Place ports and restructure all signals by going to Connectivity->Net->Restructure->All Signals.

5. Do the automatic routing like you did in Lab 5. Make sure there are no DRC errors. Correct the layout or do the placing again if there are errors. Do the layout-versus-schematic (LVS) check and perform extraction of parasitics using Calibre(PEX). The final layout should look like the one in Fig. 7.

Fig.7 Final 4-by-1 bit SRAM layout

Finish this exercise by saving designs and closing all Mentor Graphics tools.