Lab 3: Getting Started with DRC, LVS, PEX and post-layout simulation

Developed by: Zheng Chen,

Modified by: Liang Yin, Richard K Wallace,Y.Guo, Haibo He, Lily Li, Yinyin Liu

Last Modified 1/26/03


  Homework 3


INTRODUCTION: This lab exercise introduces how to verify the layout of my_inverter created in the last lab, using Mentor IC verification toolsets. This lab will cover:

  1. Design rules checking (DRC) with ICrules.
  2. Layout versus schematic (LVS) with ICtrace.
  3. Parasitic extraction (PEX) with ICextract.
  4. Post simulation with AMS

Before you go to this Lab, please check the following environment setting in your .cshrc file: 

CAL_HOME /home/mgmgr/mg07/Calibre/ss5_cal_2007.2_26.18

If the slash(/) after Calibre is missing, please insert the slash and source your .cshrc file first.

DRC with ICrules:All the other IC verification toolsets are integrated within ICStation environment. ICrules is used for design rules checking (DRC).

1) Generate Design viewpoint: in the Console window, type the following command to generate design viewpoint:

adk_dve  /home/<your user name here>/mgc/class/my_inverter

This will generate the design viewpoint. The design viewpoint are used by different applications, for example,  LVS view point. Although the different application's object is the same one created from Design Architect, their requested information is different between each other. It can be explained that these applications deal with the design object with different viewpoint.  Just like a person, who is a teacher to his students, a father for to his daughter and a son to his parents. We need to create different viewpoints for different applications. After back annotation, the design object will include the information from different viewpoints.

2) start the IC Station by input :

adk_ic

3) Open the my_inverter cell that you created in lab2 from  /home/<your user name here>/mgc/class/physical_lib directory.

4) Set your working directory by using the pull down menu, MGC>Location Map>Set Working Directory and enter:

/home/<your user name here>/mgc/class/physical_lib

5) Click on the ICrules item on the IC palette. You may have a look at which design rules will be checked, by selecting List>Checks. All the rules displayed in the dialog box are defined in the design rules file $ADK/technology/ic/ami05.rules.

6) Select the pull-down menu MGC>Setup>Session... to set sessions shown as left right tiling.

7) Open the transcript window by selecting MGC>Transcript>Show Transcript.

8) Activate the layout window by clicking on the layout screen and click on the Check item on the IC Rules palette and press [OK] in the Check DRC box. You will see all the checking results shown in the transcript window.
 

Figure 1: Design Rules Check Window

 

9) If you got design rules violations, scan these violations by selecting [Set Scan to] First and Next, and so on, which is located on the palette window.  At the bottom of the transcript a line such as (DRC compleated, Total Rule Checks:82; Total Results: 0: Total Original Geometries: 37 ... etc). The number beside Total Results signifies design Errors.

 

There maybe one error in this lab regarding VDD and GND connection. To solve this, you need to fully cover the VDD and GND with a Meral1 layer.  Refer to Lab 2 for how to put this layer. 

 

Other common errors come from the space limitation violation - please follow the design rules in the text book for reference.

        A) To edit your cell select the pull down menu File>Cell>Reserve.

        B) Correct the violations using layout editing techniques learned in Lab 2 and by following the design rules in the book (Digital Integrated Circuits by Jan M. Rabaey, page 97).

        C) DRC again until no violation is found.

        D) Save your cell. File>Cell>Save Cell.

LVS using ICtrace (M):  There exist two types of layout versus schematic (LVS) verifications, Direct and Mask. LVS compares the schematic connections you created in Design Architect to the net connections made in the IC Station.

        Direct mode compares the electrical connectivity at the current heiarchy and stores the connectivity information directly within the cell. This mode allows for top down design where subcomponents may not be implemented yet. Direct mode views subcomponents from a "Black Box" perspective.
        Mask mode compares electrical connectivity of the entire ICgraph hierarchical layout with the connectivity of the source circuit. Mask mode is the most complete connectivity checking but on large designs it requires excessive time to extract at every heirarchy.
 

    1) If the active palette is still the ICrules palette, select Back to go back to IC palette. Then select ICtrace (M) item.

    2)  Select Logic>Open: from the ICtrace (M) palette and  navigate to your /home/<your user name here>/mgc/class/my_inverter/lvs directory. This will open the schematic design viewpoint you created in Design Architect, lab 1. You can manually compare connections between the schematic and the layout, by selecting nets (interconnections) or instances (parts) in the schematic window.

    3) Select the pull down menu File>logic>close to allow LVS to perform.

    4) Click on LVS in the ICtrace (M) palette. In the dialog box, it will automatically show the Report name with lvs.rep (if it doesn't automatically show, you need to input this).  Select Source name with /home/<your user name>/mgc/class/my_inverter/lvs (design viewpoint file you created).

        A) Click on the Setup LVS... button. In the Setup LVS form change the following items and click OK

        Ground Names : VSS GND Recognize Gates : Yes

        B) Run LVS by pressing [OK] in the LVS (Mask) dialog box.

    5) When the LVS check completes, select Report>LVS from ICtrace (M) palette. If you see a cross symbol  in the report file(Figure 2), which means that this LVS failed. The errors are listed below that cross symbol, you should look at them and correct your layout .
 

 

Figure 2: Incorrect LVS
 

 

There are two errors you may have here - we use these errors to show you how to correct the LVS.

(1) In the schematic you designed in lab 1, we are using W =5 and L = 2, while in lab2 when you create the layout, we are using W=4 and L=2. Therefore, you need to change the transistor in the schematic that you created in lab 1 to W=4.  To do this, after you open the schematic in Design Architecture, select the transistor, right click the mouse, select "Properties".  you will see all the parameters related to the transistor.  select "Width = 4", click OK. and you will be asked to modify the property. Change the Value to 5.

(2) Connect the "Bulk" terminal (the arrow terminal) of PMOS to VDD, and connect the Bulk terminal of NMOS to GND.

(3) After you modifed the schematic, Check & Save.  and go to regenerate the design viewpoint. Type the following command in the Console.

adk_dve  /home/<your user name here>/mgc/class/my_inverter

After that, run LVS again, and  check Report->LVS again, you should see a smiley face, which means your layout is correct now, otherwise repeat previous steps until you see the smiley. You may use cross probing and highlighting to understand the relation between the layout and the schematic. When you select the net VSS in the schematic window, you may find that the polygon of P-well in the layout window is not highlighted, while the whole substrate is highlighted. This is because the p-well layer is not defined in the design rules.
 

 

Figure 3: Correct Lvs
 
 


 
 


Post-layout Extraction using Calibre PEX:

With the layout complete and passing LVS and DRC, it is time to extract the layout parasitic netlist. This will give you a spice netlist of your layout complete with resistance, parasitic capacitance and coupling capacitance. For the extraction process you will use Calibre Interactive - PEX.

Before you run PEX, you need to generate the netlist. Got to ICTrace (M) from the IC Palettes, click on "Netlist".  In the pop-up window, input a name for the netlist : my_inverter_netlist, keep all the other setting as default and click OK This will generate netlist for your PEX.
 

Step 1: In IC Stations menu bar, select Calibre -> Run PEX. In the pop-up window, input the Path to Calibre tree

$CAL_HOME

This will launch Calibre Interactive - PEX.

Step 2: If this is your first time running Calibre Interactive - PEX you will need to create a new runset so just click Cancel. If you have run Calibre before find the previous runset. This will simplify setting up Calibre.

Step 3: Begin by clicking the Rules button and setting the rule file and working directory. The rule file should be of the form:

$ADK/technology/ic/process/ami05.calibre.rules

The Rules button should now be green.

Step 4: Next click the Inputs button. The Layout tab should be set correctly. Under the H-Cells tab, change the PEX x-cell file path to 

$ADK/technology/adk.hcell.

Under "Netlist" tab, change the "Files" to be "my_inverter_netlist" that you generated.

Step 5: Now select the Outputs button. At the top, the Extraction Type should be Transistor Level and you can choose one of the following types:

RCC - Distributed RC network with coupling capacitors

RC - Distributed RC network without coupling capacitors

C - Lumped net capacitance with coupling capacitors

Select the first one: Distributed RC + coupling caps

Step 6: In the Netlist tab you can setup the output format and file name. Choose DSPF as the Format and Use Names From: SCHEMATIC.  You should also see there is a name for File: "my_inverter.pex.netlist".  You may change this file name to be "my_inverter.pex.netlist_DSPF" for you to remember that the output file is a DSPF format.  Remember this output file name since you will need this output file for post-layout simulation.

Step 7: Next choose Setup -> PEX Options from the menu bar. In the Netlist tab click the Ground node name: check box and enter GND. In the LVS Options tab set Recognize gates: to All. Also enter the following:

Power nets: VDD

Ground nets: GND

Step 8: You should now be all set to perform the extraction so click Run PEX. If a pop up asks to overwrite the layout file click OK to ensure Calibre sees any recent changes to your layout.

Step 9: When Calibre has completed the extraction a window will pop up showing the top level of the extracted netlist. Notice that there may be up to two additional netlists which will be included into the top level. The first will contain the RC networks and the second will contain the coupling capacitors.

Note: You should not attempt to extract your design once it has been put into a padframe.

Post-layout Simulation with AMS

 

We already covered the materials for AMS simulation in the first lab.  In this section, we will do the post-layout simulation using the PEX file you just generated. 

 

Step 1: Open da_ic (remember go to p3 first if you are in SOLARIS10), and open the schematic in your lab 1 design.

 

Step 2: Enter simulation model by selecting Analog/Mixed Signal Configuration - refer to lab 1 for detail.

 

Step 3: In the menu, select Parasitics -> Add DSPF.  Browse to the dspf file you just generated in the PEX step.  Select the Level as "RCC"

click OK. This will bring you to the post-layout simulation considering parasitics.  You will see the "..../eldonet:(DSPF + RCC)" in the top of the schematic window.  This means you are doing post-layout simulation with the consideration of PEX.

 

Step 4:  Follow the AMS simulation steps as you did in the first lab, and observe the simulation waveform.

 

Once your simulation is working properly, show the simulation results to TA. 

Note:  Finish this exercise by closing all Mentor tools.


 

[ VLSI EE415 Lab Assignment ]