Lab 2: Getting Started with ICgraph
Developed by: Zheng Chen
Modified by: Sanjeev Gunawardena, Liang Yin, Richard K Wallace, Y. Guo
Last Modified Dec., 2008
INTRODUCTION:
This lab exercise introduces how to handcraft the layout for a simple inverter, using Mentor's layout editor ICgraph. In full custom IC design, you must develop your own "standard cells" which should have both schematics at the transistor (FET) level and layouts at the physical level. We have created the schematic for my_inverter in the last lab, and here we'll craft a layout for it.
We will adopt a twin-well, 2 metal and 1 poly MOSIS Scalable CMOS process and design rules (Rev. 7 with half lambda rules).
PROCEDURE:
Notice: Before going ahead, you can make a subdirectory physical_lib under your $CLASS, where the layouts of cells will be stored.
1) After logging into a workstation in Unix lab, start command window and type in the command to invoke ICstation:
%adk_ic
ICstation is Mentor Graphics' layout editing software toolset. ICgraph is the heart of the ICstation environment. Set the working directory to $CLASS by selecting the pull-down menu MGC>Location Map>Set Working Directory.... and set it to your physical_lib folder
2) The MOSIS Scalable CMOS (SCMOS) process should be manually loaded by selecting File>Process> Load... . Enter $ADK/technology/ic/process/ami05 in the dialog box and click OK. Load the design rules by selecting File>Load Rules... . Enter $ADK/technology/ic/process/ami05.rules in the dialog box and click OK. You may open the design rules file for your information by selecting MGC> Notepad>Open>Read-only... and entering $ADK/technology/ic/process/ami05.rules as the file name in the dialog box.
3) We will need an existing cell via later. Copy an
existing via cell to your cell library by selecting the pull-down menu MGC>
Design Management >Copy Object.... Click OK on the question. In
the dialog box, from $ADK/technology/ic/process and select ami05_via,
copy to destination /home/<your
user name>/mgc/class/physical_lib/
. We'll use this via cell
later. Note: The Via cell is represented by the highlighted icon in Figure:
1. This is the only file required for your physical_lib directory. A via is
used to connect Metal 1 to Metal 2.
Figure 1: IC Station, Copy Object
4) Create an inverter cell by clicking on the [Cell] Create item on the session palette. Select Type: No connectivity. In the dialog box, enter
Cell Name: $CLASS/physical_lib/my_inverter (same name as the comp property value of the symbol, see lab 1).
Process: $ADK/technology/ic/process/ami05 and Rules: $ADK/technology/ic/process/ami05.rules
Click on Options, Select Angle Mode: 90 Cell Type: Block and Attach library: $ADK/technology/ic/process/ami05.
Click OK to select the create cell options and click OK to create cell.
In the layout editor window, you may use the default strokes (holding on the middle button of the mouse) to zoom in or out. Use menu Help On Strokes to study the strokes for zoom-in, zoom-out, view-all, view-area, and unselect, etc.. When zoomed in enough, it shows two kinds of grids, small and dim ones, as well as big and bright ones. The small grid represents 1 lambda, while the big grid represents 10 lambda. (Attention: This is different from the old version of Mentor software.)
5) Type the command sho la p to show layer
palette. In the dialog box, you may see all of the layers defined in
this process. We will only draw layouts on layers 2-3, 41-51, and 4104. So, you
could close the dialog box and type sho la p 2-3 41-51
4104 and return. The layer palette will be shown on the upper
right. Each layer has three switches "svf" to represent its
selectability, visibility, and fillability. Click the left button of the
mouse on the layer to select it. Click the middle button on the layer to
toggle its visibility. Click the right button on the layer to toggle its
fillability.
6) Figure 2 represents a stick diagram of the inverter schematic. We will follow this diagram to help create our inverter cell.
Figure 2 : Stick Diagram of Inverter
Note:
1. Do not overlap ports, devices or nets unless intended by your layout.
2. Often use unselect all (use hotkey F2 ) to make sure that you work with the proper objects.
7) Port Creation - Ports are the external connections to the device. There are 4 ports for the inverter GND, VDD, IN and OUT. Note: there is redundancy to many of the options used in IC Station. You can probably find the same command in the pull down menu's, the palette and the pop up menus. Also, for people who wish to become real speed-burners in IC Station, middle click and draw a question mark across the screen to learn about IC graph Strokes.
A) Set the IC layer to Metal1.PORT by clicking on [Metal 1.PORT] layer on the sho la p palette.
B) Click on the [shape] button located in the [Easy Edit] palette.
C) Click and drag the cursor and make a square 3 x 3 lambda. You may sometimes wish to create a ruler to determine the height and width of the square by using the pop up menu option add>ruler. You can modify any shape by using the pop up menu edit>notch or edit>slice.
D) Use the pop up menu edit>copy and place three more squares. (see figure 3)
E) Use the pop up menu unselect>all or use F2.
F) Select one of the squares. This will be your VDD port.
G) Add properties to the VDD port. The properties consist of a net name and a physical pin name. The properties modify the design by making the layers visible in an external aspect. When you include this cell in a hierarchy, you will only see the layers with the associated properties. This is to help make things clear at higher levels of the hierarchy.
i) Change the cell to connectivity editing by using the pull down menu Context>Set Cell Config>Connectivity Editing. Nets group together individual pieces of the cell under a single label. This tells IC Station that the pieces are connected together.
ii) Add net to the Metal 1 port. Select [Add Object] Property Text * from the Easy Edit palette. In the prompt bar, enter Property name: net and value: VDD. Open the [options] form, then select layer metal1.port, change the [height] to 1, [Property Owner] net, and click on [Keep options] settings button. click OK to accept the choices and move the mouse and click where you want to put the text.
iii) Add a port or physical pin to the selected item. Choose the pop-up menu Add>Make>Port. In the prompt bar, fill [type] power, [direction] in, and [name] VDD.
iiii) Unselect the port and choose another to be port GND.
Use the method above (points ii and points iii) to add the properties to the
port except the Property name: net, value: GND and pin [name]
will now be GND.
H) The last two ports will be the signal ports of IN and OUT.
i) Unselect the GND port and choose another port without properties. Give the port Property name: net, value: IN, and port [direction] in, [type] signal and [name] IN.
ii) Unselect the IN port and choose the last port
without properties. Give the port Property name: net, value: OUT and
port [direction] out, [type] signal and [name] OUT.
FIGURE 3: Port Creation
8) Device Creation: Create the NMOS transistor with a width of four and a length of two using the pop-up menu option Add>Device. Follow the hyper-link to learn more about device creation. Note: The lengths and widths of the transistors are specified in Lab 1. All devices you create must have their corresponding values specified in DA. If DA specifies different values than the IC device then any later device performance simulation will be incorrect.
A) Highlight Specify Name and hit [OK].
B) Input MN in the [Specify Name] window and hit [OK]. This means you want an NMOS device while MP represents a PMOS device.
C) Enter [width] 4 and [length] 2.
D) Choose [Mos Transistor Types] nmos4. This represents a 4 terminal device.
E) Leave sequence option unchanged,
F) press OK, and place device to where you want
G) Create a PMOS device that has a singular transistor with a width = 4, length = 2 and place the device.
H) Rotate the PMOS device 180 degrees by selecting the pop up menu item edit>rotate>180. This will place the drain of the PMOS device above the source of the NMOS device (Refer to the stick diagram of Figure 2).`
I) Activate the editor window, and select the [Easy Edit]
item on the IC palette. Add a ruler for properly placing the devices 9 lambda
apart, by choosing [Add Objects] Rulers * item. Note: look up book
(Digital Integrated Circuits, Jan M Rabaey) for more information on layout
design rules. The devices must be separated by 9 lambda because they are
surrounded by wells of different potential. Note: In the next lab you will
learn to use DRC to check for any design rules violations.
Figure 4: NMOS and PMOS Device Creation
9) Connecting the devices to the ports using the stick diagram of Figure 2: This will assign the source, drain and gate of the NMOS and PMOS devices to the nets you created for the ports.
A) Unselect all and then select the pin to the left of the gate (source pin) of the NMOS device. Note: The gate is the red Poly line intersecting the center of the device while the source and drain are the blue Metal pins to each side of the gate. You should get a message similar to the message at the bottom of Figure 4 ( Pin "s"... on a device "mn" ....).
B) Choose the pull down menu, Connectivity>Net>Add to Net option.
C) Choose [Select net name] GND and press [OK] button and you should see a yellow "overflow" line connecting the pin to the port.
D) Follow the stick diagram of Figure 2: to connect the
remaining pins to their corresponding ports.
Figure 5: Connecting the Device using the Stick Diagram
10) Creating Well Contacts:
A) You can choose either of two ways to create nwell_contact.
i) Find the nwell_contact from ADK library. In the menu, File>Cell>Open...ami05_via>nwell_contact. A cell will open, which is the nwell contact. Copy the whole cell and paste it to your inverter cell and put it at proper position.
ii) Create nwell_contact by hand. For the nwell_contact, you need to draw
a 2L x 2L square of contact_to_active, a 4L x 4L square of metal1
layer, a 5L x 5L square of active, a 9L x 9L square of n_plus_select, and a 12L
x 12L square of n_well, which are overlapped. Then store nwell_contact.
Figure 6: Nwell Contact
B) Also, you can choose either of two ways to create pwell_contact.
i) Find the nwell_contact from ADK library. In the menu, File>Cell>Open...ami05_via>pwell_contact. A cell will open, which is the pwell contact. Copy the whole cell and paste it to your inverter cell and put it at proper position.
ii) Create the pwell_contact, do the same things except using p_plus_select and p_well layer (use 11LX11L) instead of n_plus_select and n_well layer, and making port GND instead of VDD.
C) Notch the VDD and GND ports using the pull down menu edit>notch to expand the port to the width of each device and 12 lambda high.
D) Place the contacts within their respective Metal 1 port
layers.
Figure 7: Well Contact Placement
11) Connecting the Device to the Ports using Poly and Metal 1.
A) Following the stick diagram of Figure 2 connect the drain of the PMOS device to the VDD rail. Use "Easy Edit -->shape, select Mental 1 to draw the connection". After that, draw a Metal 1 shape to fully cover the VDD region, then draw another Metal 1 shape to fully cover GND region.
B) Connect the source of the NMOS device to the GND rail.
C) Create a 5 x 5 lambda square of Poly and use it to overlap a 2 x 2 lambda Contact_To_Poly square. This contact is required to connect Metal 1 to Poly. Note: the 1.5 lambda overlap of Poly to Contact and refer to the design rules in the book.
D) Create a Metal 1 shape that overlaps the port IN to the Poly contact. Note: Notice the 1 lambda overlap of Metal to Contact.
E) Connect the gate Poly to the contact by notching the gate Poly. Note: Minimum Poly width is 2 lambda.
F) Connect the source of the PMOS device to the drain of the NMOS device by a Metal 1 layer. Note: minimum Metal 1 width is 3 lambda.
G) Notch the Metal 1 strip to overlap the OUT port.
Figure 8: Final Cell
12) Finish this exercise by saving the cell File>Cell>Save Cell and closing IC station.