Lab 1: Getting Started with Design Architect and AMS Simulation
Developed by: Zheng Chen
Modified by: Liang Yin, Richard K Wallace, Jing Liang, Yongtao Guo, Feng Wang, Lily Li, Basawaraj.
Last Modified Dec., 2008
Printing graphics under Mentor enviroment:
Currently, you can't directly print your graphs in mentor software using the
plot menu. However, there is one way to get it around,
right-clik on desktop, choose Application->snapshot, to hardcopy what
you want and save it as JPG files, and print it.
INTRODUCTION:
Before going ahead, please make sure that you have set up the environmental variables properly via the instructions in the requirement of VLSI Lab. In this lab exercise, you need the soft path $CLASS to be set in advance. For example, you may link $CLASS to $HOME/mgc/class ($HOME must be the full path such as /home/<your name>, and you should make a sub directory class under mgc). (Note: Sourcing the setup file will change the $CLASS to $SHARE). If it is not the first time for you to use Design Architect, you may find this lab exercise is pretty easy. However, you need to finish it before you can do the later ones.
This lab intends to illustrate the traditional front-end logic design procedure for VLSI, by developing a very simple inverter into your own logic parts library. In the meanwhile, you will learn how to start with Mentor Graphics design entry toolsets Design Architect, and simulator AMS. This lab will cover:
Schematic capture:
· After logging into a workstation, start running DA(Design Architect) by type in:
% da_ic
In DA, create schematic sheet for a CMOS Inverter,
a. Click on the Schematic
icon on the session palette that resides upon the right hand menu.
Figure 1: DA window
b. Enter component name: $SHARE/my_inverter in the dialog box.
c. Select the pull down menu MGC>Location Map Set Working Directory and enter $CLASS. NOTE: It is extremely important to always set your working directory before you use ANY tool in mentor graphics. Failure to do so can place your work into unwanted directories. It is a good idea to create the habit of first setting your working directory before you do any work in any tool of Mentor Graphics. If you do accidentally place your work into an incorrect directory only use Design Manager to move the files into their correct directory. Do NOT use command line editing to move parts around. Parts have many hidden links that the Design Manager will automatically update upon any move.
d. Click ADK IC Library icon on the session palette.
Figure 2
e. To construct an inverter, you need 1 NMOS transistor, 1 PMOS transistor, 1 VDD, 1 GND, 1 portin and 1 portout. Select these parts from the palette, and place them in the schematic window.
f. In the right palette window, hold on the right mouse button and select the Display Schematic Palette item in the popup menu to go back to the main menu. Click on the ADD>WIRE icon to connect the parts in the editor window as the figure on the right shows. Double click to end a wire connection. You may need to move some parts to proper positions.
g. Unselect all by clicking the corresponding button on the right palette and select the portin and portout. Select the popup menu (Right click on the window) Properties>Change Text Values... and enter In and Out as net names in the dialog box. Then click on the portin's name NET to change it to In, and click on the portout's name NET to change it to Out.
Figure 3: Properties Menu
Figure 4
h. Click ADK IC Library again. Select DC from Sources, and place it on the schematic. Add VDD and GND to it as shown in Figure 5. Select the DC, select the popup menu (Right click on the window) Properties>Add…
Figure 5
In the popup menu, select DC from Existing Property Name, and enter 5V in the Property Value. Click OK.
Figure 6
Figure 7
i. Check your sheet by click Check & Save from the Schematic Palette. If there are any errors correct them and check again.
Symbol creation:
1. Both its function and its symbol should represent every logic component in your part library. In this lab exercise, the inverter's function is defined by the transistor level schematic created in the previous step. Now we create a symbol for this inverter, which can be chosen in a higher level schematic to construct a bigger design.
a. Activate the inverter's schematic sheet. Create symbol from the pull down menu Miscellaneous>Generate Symbol.... In the dialog box, click on OK without changing all defaults.
Figure 8
b. In the symbol window, delete the default box body of the symbol. DO NOT REMOVE THE PINS. Click on the ADD POLYGON, ADD CIRCLE, and ADD POLYLINE icons to craft the symbol that looks like the figure on the right. You may need to move the pins to proper positions.
c. Highlight only the symbol body (triangle). Select the popup menu Properties>Add.... In the dialog box, click on the add new row icon, enter Property Name with COMP and value with MY_INV. Make the value visible. Move the ghost "MY_INV" to a proper position. Select the same popup menu again, click on the add new row icon and enter MODEL as name and INV as value. Make this value hidden by deselecting the Visible? icon. This property will tell simulation this symbol represents an inverter.
Figure 9
d. Check and save your symbol by clicking Check & Save. If no errors found, close the symbol before continuing.
AMS simulation:
1. Now we will do the functional
simulation for this inverter. Click the green triangle on the left menu. Select
Analog/Mixed Signal as simulation type. Click New Configuration and
select AMI05. Enter a Configuration Name, such as Lab1_configuration.
Click OK.
Figure 10
Figure 11 shows the interface after entering the simulation mode.
Figure 11
2. Click Session, and choose Netlister…
Figure 12
3. On the popup menu, change default setting GROUND to GND.
Figure 13
4. Click Lib/Temp/Inc, select Libraries. Select Library Type as Spice, give a name, test1, for the scenario name and click on Add Scenario to List icon. Click on browse for library icon, works only if the added scenario name is highlighted. Navigate to the Path: $ADK/technology/ic/models and select ami05.mod. Click OK. Close the Setup simulation window.
Figure 14
5. Click Analyses…, select Transient.
Figure 15
6. Add force to the input node. Select the
input node. Click on Forces and choose Manager. Selcet Independent-> Pulse
as the type. Set the Pulsed Value to 5 if you want the input
level to be high, or 0 if you want the input to be low. You can change
the Rise Time, Fall Time, Pulse Width and Period. Now click on Add Force icon
to add this force to the input node. Close the setup simulation window.
Figure 16
7. Select the input and output nodes you want to observe. Click Wave Outputs icon on the left side palate to open the setup simulation window. With both the objects selected, select Analysis as “TRAN”, Task as “Plot”, Type as “Voltages” and click on the “Add Wave Output” icon to add both the objects. Close the setup simulation window.
Figure 17
8. Run the netlist. Click Netlist under Execute.
9. Run simulation. Click Run ELDO under Execute.
Figure 18
10. At last, view the simulation waveforms by clicking X Probe under Result. Choose Voltages-Default. The simulation waveform window will popup.
Figure 19
3. End simulation by clicking on End Sim. Finish this exercise by closing Design Architect.
Lab Homework
The next lab involves the physical creation of the inverter device. This is done by designing a device "cell" by using of a Mentor Graphics tool called IC Station. IC Station is a powerful CAD tool that not only lays out the cell but also analyzes the cells electrical properties. These properties consist of the resistive and capacitive effects that are determined by how you size the NMOS and PMOS transistors. The properties are also affected by how you interconnect the transistors. These properties will be stored in an ASCII file and with the use of the Mentor Graphics tool called AMS the design engineer can predict the final behavior of the device.
To help the student understand cell design three documents have been written. These documents must be read and understood before working on Lab 2. Each document is based upon a cell design methodology called Complementary Static CMOS design.
The first document discusses the general properties of CMOS transistors and how to create schematics of any function in Complementary Static CMOS format. The task is to create a device with a specified logic function EG: F = AB + C + DE.
How to design Complementary Static CMOS Devices.
Once the schematic is made the component transistors must be sized properly. The second document discusses sizing the NMOS and PMOS transistors within your schematic. Device sizing determines the height and width of the transistor gate and will directly affect how your device will perform.
How to size transistors in Complementary Static CMOS devices.
Finally, the design engineer needs to have a conceptual model for the layout of the cell. Stick diagrams provide rough sketches of the ordering of the individual transistors as well as where to route the interconnections. The third document will prepare you to create stick diagrams.
How
to create stick diagrams in Complementary Static CMOS devices.
[ VLSI EE415 Lab ]