Doulos
VHDL/Verilog Page (uk)
Methodology
for the modeling and simulation of microsystems Dr. Romanowicz
Distributed
Simulation of hybrid systems / integrated circuits (Analog/Digital)
VHDL-AMS
as a Discrete and Continuous Time Modelling and Simulation Language
SPICE To VHDL-AMS TRANSLATOR (SPAMS)
VHDL
1076.1: Analog and Mixed Signal Extensions for VHDL
EDA
at ECS, University of Southampton, UK