Completed ProjectsPresentations (Power Point)The motivation beyond this research is to discover knowledge represented by observations and to apply this knowledge to object recognition by developing theory, designing algorithms, and building architecture for neural networks or reconfigurable processing hardware.
Wavelets and other linear and nonlinear transformations of the input space are used to preprocess the input data. Feature extraction is performed using the above mentioned transformations and statistical properties of the transformed input data are captured at the training phase and used at the classification phase. The entropy based mutual information index is used to monitor the training process and to optimize the transformation of the input space. Bounds for the extracted information are estimated based on the estimation error of the probabilities used to evaluate system entropy.
Designed transformations and classification algorithms are implemented in the self organizing reconfigurable architectures based on programmable gate arrays. Marginal classifiers and rough sets are used to describe the theoretical foundation of the machine learning process. Hardware description languages and synthesis tools are used to describe and synthesize the designed architectures. Dedicated mixed signal neural networks are designed and built using VLSI technology.
Clustering can be performed as self organizing process in which points are grouped into clusters based on statistical properties of minimum distance between points in a single cluster. This way the number of clusters is automatically determined and local statistics is dynamically updated as clusters grow. This approach was successfully implemented to SAR based target recognition. In this project a concept of piecewise linear templates was used to improve classification results.
Machine learning benefits from automatic feature extraction. This can be done in many ways. Our new approach was using iterated wavelets for feature extraction. The iterated wavelets use a simple Haar wavelet hardware to evolve into a unique transformation useful for classification of trained signals. Choosing the best features from a given set is also a challenging task particularly for large size of databases. A unique approach developed at Ohio University uses rough set theory and marginal reducts to accomplish an efficient feature selection, and problem classification.
In neural network applications, designed transformations and classification algorithms are implemented in the reconfigurable architectures based on programmable gate arrays. Hardware description languages and synthesis tools are used to describe and synthesize the designed architectures. And an example project is presented at FPGA Realization of Haar Wavelett for Pattern Recognition.
A new evolvable hardware organization and its learning algorithm to generate binary logic artificial neural networks based on mutual information and statistical analysis was developed. Thresholds to convert analog signals of the training data to digital signals were used. In order to extract feature function for multidimensional data classification, maximum information was calculated in each subspace. Next, dynamic shrinking and expansion rules are developed to build the feed forward neural networks. Hardware mapping of learning patterns and on-board testing were implemented in Xilinx FPGA.