The input / output portion of the motherboard is described above in a simplified flow diagram. The motherboard is designed so that any module can plug into any one port at a time. This allows any combination of modules to be used at any given time. The reason for dividing up the ports into banks of 32 is because the CPU QSPI buffer can only handle a maximum of 32 bytes at a time. Each module or daughtercard will have custom sample rates that can be modified at run-time by the end user. To accomplish this, all of the ports must be sampled at the fastest sampling frequency and only the required data is kept. The rest is discarded and the next sample is made.
The actual data latching operation is rather complicated to explain due to several things occuring at once. The Mod Latch line goes high signalling the input modules to present their data to the module bus. Once the MB Latch line and the E0 line rises, the data is latched and ready to be shifted in. The MB Latch drops and the toggling Clock starts the data shifting process. While the input data is shifted into the CPU, the output data is getting cycled into the latches. After the transfer process has finished, the Mod Latch line goes low to lock the output data in the output modules. All signal lines between the CPU and motherboards are filtered with a schmitt triggers to reduce the chance of noise affecting the switching process.