Lab 2: CMOS Operational Transconductance Amplifiers

-by: Zheng Chen

Last Modified 4/29/97

INTRODUCTION:

In this lab exercise, we will design a simple two-stage CMOS opamp and a wide-range current-mirror OTA.

We have known how to use Design Architect and AccuSimII to design and verify the transistor level circuits. In this lab, we will go further to do layout design for the wide-range OTA using full-custom procedure in IC station. You may refer to the on-line IC Station User's Manual for more details about IC layout design. This lab will cover:

  1. Transistor level design with Design Architect.
  2. Analog simulation with AccuSim II.
  3. Layout design with IC graph.
  4. Parasitic extraction and backannotation with IC verify.
  5. Post simulation with AccuSim II.

    Transistor level design with Design Architect:

  1. After logging into a workstation in Stocker 301 (barney, lisa, krusty, maggie, marge, or skinner), start running Mentor Design Manager:
      2. % dmgr&

    Invoke DA by clicking on design_arch icon in the tools window.

  2. In DA, create schematic sheets for a simple two-stage opamp and a wide-swing current-mirror opamp.
    1. Set the working directory to your $CLASS/parts.
    2. Open new sheets $CLASS/parts/ts_opamp and $CLASS/parts/wr_opamp which correspond to the two-stage opamp and the wide-range opamp, respectively. Use the techniques in Lab 1 to create these two opamps shown in Figure 1 and Figure 2.

      3. Figure 1. Simple Two-stage Opamp
      Figure 2. Wide-range Current-mirror Opamp
    3. In Figure 1, transistors Q1 ~ Q5 construct a differential pair as the input stage, while Q6 and Q7 construct a common-source amplifier as the output stage. Frequency compensation of the opamp is accomplished by means of the capacitor shown in Figure 1. In a real design, a "nulling" resistor, which is usually created by a transistor, in series with the capacitor has to be added to make the opamp more stable in a feed-back configuration.
    4. In Figure 2, three current mirrors are constructed by Q3 and Q5 (1:2), Q4 and Q6 (1:1), and Q7 and Q8 (1:2), respectively. This kind of current-mirror opamp has higher unity-gain frequency and wider output voltage range than a simple two-stage opamp.

    Analog simulation with AccuSim:

  3. Perform frequency response analysis on the opamps using AccuSim II.
    1. Before invoking AccuSim II and using SDL procedure in ICgraph, you need to generate the sdl design viewpoint as you did in Lab 1.
    2. Invoke AccuSim II and perform ac analysis as you did in Lab1. For the first opamp, set VB to dc value 3.96 V which generates bias current of 100 micron ampere on Q5. Give V- dc 2.5 V and V+ ac 1 V with offset 2.5 V. Start from 100 Hz and stop at 100MEG Hz. Figure 3 shows the frequency response of this simple two-stage opamp. For the second opamp, set VB to dc 0.8425 V, which generates bias current of 160 micron ampere on Qb. Set V+ and V- the same as the above. Start from 100 Hz and stop at 1G Hz. Figure 4 shows the analysis result.
      3. Figure 3. Frequency Response of the Simple Two-Stage Opamp
      Figure 4. Frequency Response of the Wide-Range Current-Mirror OTA
    3. From the above figures, we see that ts_opamp has unity-gain frequency bandwidth 23.3M Hz while wr_opamp has nearly 800M Hz. The latter has -3dB frequency of 27M Hz. The former has more than 60dB gain in 22.6K Hz bandwidth.
    4. Remember to save the setup data for later use.

    Layout design with ICgraph:

  4. Layout for wr_opamp. Before you can go through the layout design procedure, be sure you have created an sdl viewpoint for your circuit. You only have to do this once per design. Even if you make changes to your design you don't have to do this again. Now you are ready to invoke ICgraph by selecting the ic icon in the tools window of Design Manager. After the ICgraph is invoked, the process and design rule files are automatically loaded. Use the notepad to view the 0.8 micron design rule file $MGC_HEP/technology/ scn08hp.rules. Note this 0.8 micron process has 3 metal layers rather than 2 metal in 1.2 micron process that we used before.
    1. In ICgraph, set the working directory to your $CLASS/physical_lib. You may set up more options, especially the UNDO level, via the pull-down menu Setup>IC.... Show the physical layers by typing sho la p 2-4 41-51 61-62.
    2. For your convenience, you may first create two cells for well contacts. Use the techniques that you learned in EE415/515 labs to create cells nwell_contact and pwell_contact. For the nwell_contact, you only need to draw a 2L x 2L square of contact_to_well layer, a 4L x 4L square of metal1 layer, a 5L x 5L square of active layer, a 9L x 9L square of n_plus_select layer, and a 12L x 12L square of n_well layer, which are overlaped one by one. Make the metal1 square a port named VDD. For the pwell_contact, do the same things except using p_plus_select and p_well layer instead of n_plus_select and n_well layer, and making port VSS instead of VDD. Save these two cells without DRC. You will use them later.
    3. Now select the [Cell]Create option on the palette menu to create a new cell wr_opamp (same as the symbol's name). In the dialog box, enter cell name wr_opamp and select GE under operational configuration for general editing mode.
    4. Once the empty cell has been opened, you should go to the Easy Edit menu on the palette menu. You may open a schematic window by selecting the pull-down menu File>Logic>Open to specify the logic source. Use the navigator to select the $CLASS/parts/wr_opamp/sdl viewpoint. Your schematic should appear in a window. You may rearrange the two windows so that they don't overlap.
    5. The first thing you should probably do is to add the mos transistors. Because we are using very large transistors, we need to fold the large transistor into small ones. You may notice that the width of the transistors in Figure 2 is multiple of 10 micron, for instance, Qb's width is 30 times of 10 micron. Let us first use a device generator to generate a folded Qb. Select the pop-up menu Add>Device: and specify the device name as mos. In the dialog box, define width as 25 lambda (10 micron) and length with 4 lambda, select nmos4 as the transistor type and both for Source/Drain Contacts, and give 30 1's in the blank boxes after the Gate Combinations item. Then you will see a long row of transistors in the cell window as shown at the bottom-right corner in Figure 5.

      6. Figure 5. Layout of wr_opamp
    6. You may copy Qb for Q1 and Q2 due to the same size. In Figure 5, the Q1 and Q2 overlap each other at the edge and are placed in the middle of the figure. You may conbine Q7 and Q8 into one device which has 18 gates. In Figure 5, this device is overlapped by Qb at the edge (the bottom row of transistors). Then generate Q3 and Q5, Q4 and Q6 using pmos4 type (the top row shown in Figure 5). The total number of pmos transistors is 30.
    7. After the placement is finished, we only need to wire up the devices using poly, metal1, metal2, via and contact_to_poly. You may use the [Add] Path item on the palette. For example, we are going to wire up the VB signal by adding paths to connect all of the 30 gates of Qb. Select the poly layer and click [Add] Path item. On the prompt bar, click on the Option button to change the path width to 4L. Then, add wires to connect the gates. You will see the path centered with a line. Note poly spacing = 3L in this 0.8 micron process. For Qb, the sources of gates are wired up together while the drains are wired up together. You may use the same pattern for wiring up transistors Q3 ~ Q8 (in Figure 5, can you tell which are Q3, Q5, and Q7?). The differential pair Q1 and Q2 are wired up in different way. In Figure 5, can you tell the drain and the source of Q1 and Q2?
    8. Once you finished to wire up the gates, you need to place some tub-ties or sub-ties using the previousely generated nwell_contact and pwell_contact. Use the techniques you knew to add ports for the input and output signals and power rails.
    9. Now it is time to see if your circuit passes the DRC. Go back to the Session palette and then select ICrules. Do a check of your circuit and then use the scanning menu items to locate the errors, if any. You should fix all DRC errors before moving on to the next section.
    10. Once all DRC errors are fixed, save your cell.

    Parasitic extraction and backannotation with ICverify:

  5. Do the LVS to your wr_opamp. Use ICtrace (M) with logic source $CLASS/parts/wr_opamp/sdl, and set LVS as not recognizing gates. Although the transistors are large, the number of nets and transistors is not big so that you may not meet many LVS errors.
  6. After your layout passes the DRC and LVS, you are ready to backannotate parasitics and/or generate a netlist for simulation using ICextract (M). In this lab, we will extract for analog simulation (AccuSim II) . Hence, lumped extraction is what you will be performing. Lumped extraction will treat each distinct net as one lumped capacitor and/or resistor. Therefore, every point on the net will see full extracted RC delays.
    1. To prepare for extraction, be sure your cell is reserved for edit. Go to the ICextract(M) palette menu and select Lumped from the palette menu to display the extraction dialog box.
    2. In the dialog box, click YES for Backannotation, and Specify Schematic Source. Give the source viewpoint $CLASS/parts/wr_opamp/sdl.
    3. Click on the Setup LVS... button and check to be sure that the recognize gates option is set to "No."
    4. Specify the name of a BA file, which will be stored with the viewpoint. A suggested name is lumped but you can choose anything. If you choose a previously used name, then you should also select the "Yes" button under the Clear option to remove any previous annotations. Alternatively, you can have several BA files where the most recently created one is used until you change the BA file in DVE, yourself.
    5. Now it is time to select the parameters to backannotate. AccuSim will use the cpl_cap_net property, which is created by saying YES for Coupling Capacitance option, for net capacitance between a node and any others. This is what you will use. The lumped capacitance can also be used but only if you are using GND as opposed to VSS and you change the property name to cap_net from the default icap_net. Lumped resistance is not used in AccuSim, so no point in extracting it, here.
    6. Accept this dialog box and extraction will begin. When the extraction is done, you will see that your schematic is automatically updated and you will see the annotations on it.

    Post simulation with AccuSim II:

  7. The final step in the design process is post-layout simulation. We will use the backannotated viewpoint to re-simulate in AccuSim II to see see if the performance of the circuit is degraded due to the real parasitics.
    1. Invoke AccuSim II on your wr_opamp/sdl as you did before. You will see annotations in the schematic window.
    2. Load your saved setup which has the windows and parameters from your previous simulation run. Use File>Simulation>[Restore] Setup data... to load the asim_setup file.
    3. Now type run to run the simulation, again. Figure 6 shows the frequency response of the backannotated circuit. You may notice that -3-dB frequency is reduced to 16M Hz and the unity gain frequency is reduced to less than 400M Hz.

      4. Figure 6. Frequency Response of the Wide-Range Current-Mirror OTA after Layout Design

  8. Finish this exercise by closing all Mentor tools.